1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device capable of avoiding damage by electrostatic discharge (ESD) phenomena.
2. Description of the Related Art
Generally, in a semiconductor device, an input circuit includes a first external terminal and an input resistor formed by an N-type impurity diffusion region connected to the first external terminal. On the other hand, an internal circuit such as an N-channel MOS (broadly, MIS) transistor has an N-type impurity diffusion source region connected to a second external terminal, an N-type impurity diffusion drain region, and a gate electrode therebetween. In this case, the drain rather than the source of the MOS transistor faces the input resistor (see: JP-A-59-87873). This will be explained later in detail.
Therefore, when a negative electrostatic pulse with respect to the second terminal is applied to the first external terminal, electrons are injected from the input resistor into a semiconductor substrate. Accordingly, the electrons are diffused and some of them reach the source region of the MOS transistor. As a result, the electrons injected into the source region serve as an energy source due to a high electric field in the periphery of the source region, thus destroying a gate insulating layer and the like. Particularly, if the MOS transistor has a lightly-doped drain (LDD) configuraturation, some of the electrons reach an N.sup.- -type region of the source region, so that the N.sup.- -type region may be destroyed.
In the above-described prior art semiconductor device, however, in order to avoid the destruction of the gate insulating layer, the source region and the like, a distance between the input resistor and the internal circuit has to be very large, for example, about 100 .mu.m to 300 .mu.m, thus reducing the number of electrons reaching the source region. Here, a minimum value of this distance is called a critical distance. The larger this distance, the larger the amount of dead space where elements cannot be arranged occurs.
Thus, the prior art semiconductor device is disadvantageous in terms of integration.